1. Field of the Invention
The present invention relates to an RF receiver for receiving digital data and more particularly to voltage reference stabilization circuitry therefor.
2. Description of the Prior Art
A block diagram of a prior art FM receiver is illustrated in FIG. 1. The receiver comprises the antenna 2 which receives an RF signal and transmits it to the front end 4 where the RF signals are amplified and converted into a first intermediate frequency (IF) signal by an RF amplifier and first mixer, respectively. The output of the front end 4 is directed to the back end 6 where the first IF signal is converted by a second mixer to a second IF signal. The second IF signal is amplified, limited, filtered and demodulated to produce an audio output signal that represents the coded binary data. The output of the back end 6 is capacitively coupled to a data limiter 8 via the capacitor C1. The capacitor C1 compensates for variations in the voltage differential between the output of the back end 6 and the limiter 8 input from unit to unit that result from component variations, tuning of the FM demodulator, and manufacturing processes. In addition, the capacitor C1 provides for a level shift between the output of the back end 6 and the limiter 8 input. The data limiter 8 converts the low amplitude audio signal from the back end 6 to logic level decision functions. The resistors R1 and R2 are used to bias the data limiter 8. The output of the data limiter 8 is directed to additional data processing circuitry and clock 10 for further desired processing. The FM receiver also includes a first switching means comprised of the transistor Q1, bias resistors R3 and R4, first driving transistor Q2 and base resistor R5. The transistor Q1 is connected between the various components of the FM receiver and the power supply and is periodically turned on and off by the driving transistor Q2 to provide a battery saving feature. The base of the first driving transistor Q2 is connected through a resistor R5 to the data processing circuitry and clock 10 which strobes the first driving transistor Q2 on and off in accordance with the timing chart shown in FIG. 3B. This battery saving technique is well known to those skilled in the art. A second switching means is comprised of transistors Q3 and Q4, bias resistor R6, load resistor R7 and bias resistor R8 and is used to precharge the coupling capacitor C1. The transistor Q3 is turned ON and OFF by the driving transistor Q4 and provides a low impedance path to charge the coupling capacitor C1 during the precharge pulse ON time, in accordance with the timing chart shown in FIG. 3C. The base of the second driving transistor Q4 is connected through the resistor R8 to the data processing circuitry and clock 10 which strobes the second driving transistor Q4 ON and OFF. The strobe signals for driving transistor Q2 and Q4 are normally derived from a fixed reference clock which is part of the data processing circuitry and clock 10. The data processing circuitry and clock 10, or portion thereof, is normally kept active during the periodic switching on and off of the various components of the FM receiver.
Normally in situations where it is necessary to pass digital data from the back end 6 to the data limiter 8, C1 will be a relatively large value. Thus, a long time in comparison with the ON and OFF switching of the battery voltage is required to charge the capacitor C1, especially when it is connected to a high impedance such as the bias resistors R1 and R2 for the data limiter 8. The second switching means is used to alleviate this situation by providing a momentary low impedance charge path immediately upon receipt of power from the battery, that is when the first switching means is turned ON. Thus, data decoding of the received bit stream can begin upon turning OFF of the second switching means and continue until the battery voltage is again interrupted by the first switching means.
However, one problem still exists even when the coupling capacitor C1 is precharged. During the precharge cycle, the receiver circuit is activated and data is present at the output of the back end 6. Thus, the voltage at the output of the back end 6 is dependent upon the data pattern being received. However, it is desirable to precharge the capacitor C1 to the difference between the voltage at the limiter input and an output reference voltage from the back end 6 that is centered between the "1" and "0" voltage levels associated with binary data reception. This reference voltage should equal the voltage at the output of the back end 6 when unmodulated carrier is received. When the output of the back end 6 is not at the unmodulated carrier reference voltage, that is when a long string of ones (or zeros) is received immediately before the turning OFF OF the second switching means, the DC voltage across C1 is decreased if a large number of ones are received (or increased if a large numberof zeros are received). Thus, relatively substantial DC voltage offsets from the desired unmodulated carrier reference voltage still occur. This will result in erroneous outputs from the data limiter 8 and ultimately result in the end user receiving no message or an erroneous message which differs from the originally transmitted message.